The present invention relates to direct memory access controllers, and specifically to controlling task execution in a direct memory access controller by maintaining an execution interval.
Direct Memory Access (DMA) controllers are used in computer systems to offload repetitive data movement tasks from a processor in a data processing system. As multiple input devices and multiple memory storage locations may exist within a data processing system, the DMA must coordinate the performance of difference tasks over time. A key concern in this coordination is to maximize the throughput of the DMA unit.
In an embedded system, it is desirable to balance the various types of utilization and avoid throughput bottlenecks. The processing time as well as bus bandwidth influence the throughput. Most designers estimate processing time and bus utilization. These considerations apply to data-communication channels, shared memories, mass-storage devices, and so forth.
Many DMA controllers have dedicated channels, each coupled to a specific input device. In this case bus bandwidth may be allocated to each of the the devices, where each device is limited to a certain percentage of the bandwidth or a maximum bus ownership timer percentage.
Many requestors are for random and nondeterministic activities that disrupt the scheduling and decrease throughput. Typical systems assign activities to groups according to throughput using a deterministic scheduling means and calculate the throughput left for random ones. These timing control mechanisms do not reflect the tasks and functions performed within the DMA controller.
Some of these processing throughput requirements are on an on-going basis, and others only occur under specific circumstances. The on-going processing tasks, which often occur on a random basis, such as in response to receiving data from a communication channel, usually are abstracted to an average processing overhead. So, based upon the speed of the communication channels and what has to be done to that channel""s data, it is possible to estimate an average percentage of the total available processing bandwidth.
Once the on-going background processing is accounted for, each set of circumstances under which the system can operate may be considered. That might include, for example, scanning a keypad searching for user input versus processing that user input. For example, if the background tasks consume about 20% of the available processing throughput, then each of the remaining tasks must take no more than a total of 80% of the available processing time.
For DMA processing, a timer waveform with a varying pulse width can be used to periodically cause a given processing task. When the waveform from the timer goes high, the DMA controller schedules processing and discontinues processing when that timer waveform goes low. However, higher-priority DMA processing may preempt the DMA controller from actually beginning the processing when the rising edge of the timer waveform schedules it to run. This non-period preserving timer assumes that once the process begins it will run for an allotted amount of time. A problem exists as stopping the timer acts to stretch out the period of timer over which processing is allowed and distorts the percentage of time allocated to that task. Non-period preserving timers ensure that the predetermined percentage of processing time is available but do not ensure that this percentage is within a predetermined interval.
Another approach used on typical multitasking operating systems to bandwidth scheduling uses a periodic timer to allow a different task to run. These timers do not specify how frequently a task runs. This is useful for applications that require specific timing intervals that are smaller than the scheduler tick, or are not easy multiples of the scheduler-tick""s period.
A need therefore exists for a task-execution timing scheme allowing deterministic processing time of tasks within the DMA unit and a method of controlling task requestors to a DMA that calculates the processing power and ability for a given condition and adjusts the throughput for a variety of devices. Still further, a need exists for a method of allocating time to tasks and preserving the period of timers for a DMA. Also a need exists for a method of and timer for bandwidth scheduling that specifies how frequently a task runs.